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功率循环是对功率半导体器件老化失效规律进行研究的关键实验方法。现有方法需要在每次循环加热电流切除时在线测量器件的结温与热阻，以监测其老化程度。由于每次循环的加热时长通常很短，这样测得的热阻并非器件的稳态热阻，而是与加热时长相关的瞬态值。以这样的热阻作为老化指标准确性不足，容易造成对器件老化情况与预期寿命的误判。针对上述问题，本文提出了一种在功率循环实验升温过程中，在线测量结温与瞬态热阻抗曲线的老化监测方法。以大电流下的导通压降作为温敏电参数测量升温过程结温，并在器件自热状态下对温敏关系式进行快速整定与更新，确保了测量的准确性不受器件老化的影响。所提出方法基于功率循环原有实验设备即可实现，通过在线监测瞬态热阻抗曲线的变化，更准确与全面地反映了器件的老化情况。

光伏并网变流器作为新能源发电系统的核心装备，其可靠性直接决定系统的安全运行与效能发挥。基于服役工况模拟的可靠性测试技术，能够在设计初期灵活复现变流器运行过程中的电热应力，已成为新能源领域关键的研发测试手段。然而，服役工况模拟系统采用的对拖测试架构因共用直流母线，会不可避免地引入零序电流通路，导致电流采样结果出现误差、模拟波形发生畸变。目前，工况模拟系统中零序电流的形成机理与影响机制尚未明确，严重制约了该方法对变流器电热特性的高精度模拟。针对这一问题，本文建立了光伏并网变流器服役工况模拟系统的高、低频零序电流时域模型。基于所建模型，深入探究了低频零序电流谐波导致电流波形畸变的影响规律，与高频零序电流纹波导致系统电流采样出现误差及零轴控制输出失真的低频化影响机理，为服役工况模拟系统中零序电流的抑制奠定了坚实的理论基础。

模块化多电平换流器（MMC）因其模块化、易拓展，且输出波形良好等优势，被广泛应用于中高压柔性直流输电系统。但随着系统功率与电压等级的不断提升，MMC面临的可靠性挑战日益严峻。阀段等效试验方法作为一种高效验证技术，通过搭建相比完整系统更为简化的试验电路，模拟被试阀段实际运行中的电热应力，从而进行各项可靠性验证试验。然而，现有阀段等效试验方法在复现暂态过负荷和交直流故障等复杂动态工况时，仍存在动态过程复现精度不足、试验电路结构复杂以及工况调节灵活性受限等问题。为此，该文提出一种基于虚拟MMC模型嵌入式控制的MMC阀段动态工况模拟试验方法，通过将可灵活配置的虚拟MMC模型嵌入试验系统控制环路，实时生成高精度动态工况参考值，无需依赖额外暂态发生装置或复杂电源结构，即能准确复现功率阶跃、子模块投切及故障穿越等典型动态工况。该方法支持动态工况参数与类型的灵活编程，可有效验证不同控制策略对MMC阀段可靠性的影响。仿真和实验均验证了该方法的有效性，为MMC阀段可靠性评估提供了一种灵活且准确的试验手段。

Advanced assess and test close to real field operation are of great significance to ensure the reliability of Modular Multilevel Converter (MMC). Thus, Mission Profile Emulator (MPE) is proposed as an economical and efficient testing scheme, which aims to create emulated mission profile to submodules (SMs) of MMCs with simplified testing circuits. A challenge of MPE is to create testing current which has as small level of current ripple as the arm current in MMC. To limit the current ripple of the testing circuit, the existing methods try to increase the filter inductance of testing circuit. However, when the filter inductance increases to a certain level, the influence from the increase of filter inductance will be offset by the increase of DC supply voltage, and the current ripple will not be reduced anymore. As a result, a new MPE with resonant filter is proposed to further reduce the current ripple, meanwhile, a control strategy and a design method are proposed to cope with the resonant filter and achieve higher emulation accuracy. Simulation and experimental results are presented for the validation of the proposed method.

With the widespread integration of photovoltaic (PV) power generation into power grids, the reliability of PV converters is becoming crucial, and there is an urgent need for comprehensive testing before PV converters are put into field operation. Due to complex mission profiles, significant challenges have been experienced to reliability testing. A mission profile emulation (MPE) system, involving a three-level neutral-point-clamped (NPC) converter and a two-level converter, is proposed as a promising method for new approaches of converter testing, offering programmable mission profiles, improved testing efficiency and reduced testing costs. Typically, to reduce power loss, DC links of two converters are connected to achieve power circulation, which inevitably creates zero-sequence current, as can be classified as high-frequency zero-sequence ripples and low-order zero-sequence harmonics, and will further result in current distortions. However, in terms of MPE system with different converter topologies and mismatched carriers, mechanism of zero-sequence current excitation remains unclear, and potential sampling distortions and control errors have seldomly been studied. In this paper, the mathematical model of zero-sequence current in MPE system with different converter topologies and mismatched carriers is established. Impacts of zero-sequence current, including waveform distortions, sampling distortions and control errors, are also discussed in details.

The grid-interaction stability of the converter may vary with grid impedance conditions, and needs to be validated before field deployment. To facilitate stability tests toward grid-connected converters, a dual-frequency-band grid emulator has been proposed, which consists of an impedance-forming converter (IFC) switching at high frequency, and a power-supporting converter (PSC) switching at low frequency. Normally, the IFC is used to mimic the terminal characteristics of a predefined grid condition, while the PSC is expected to absorb/supply the power flowing through the converter under test. However, due to the limited control bandwidth of PSC, a large proportion of harmonic and transient power may flow through IFC under grid resonance conditions, which deviates from the design expectation. This may lead to overcurrent of IFC and limit the full use of PSC's power capacity. In this article, the power sharing of a dual-frequency-band grid emulator is studied, and an enhancement method utilizing the inductive terminal characteristic of IFC is proposed. With the proposed method, the current tracking performance of PSC is elevated, which naturally improves power sharing and extends the applicable power range of the grid emulator.

In a power-electronics-based mission profile emulation (MPE) system, the converter under test (CUT) and the emulating converter are typically powered by the same dc voltage source for high efficiency. This also inevitably creates a circulating path for common-mode current ripples, which will cause sampling distortions and control errors. The current ripples have not been adequately addressed in the existing literature on the MPE. Typically, the common-mode current ripples can be suppressed by common-mode chokes. However, the amplitude of the common-mode current ripples fluctuates with the difference between the carriers of the CUT and the emulating converter, burdening the common-mode choke. The carrier difference can be fixed by synchronizing the carriers of the CUT and the emulating converter. However, conventional synchronization methods require modifications to the CUT, which changes its characteristics and prevents the MPE system from being plug-and-play. In this article, an active pulsewidth modulation synchronization method with on-off-state information of devices in the CUT is proposed. The carrier of the CUT can be reconstructed without modifications to the CUT. Then, the carrier of the emulating converter can be synchronized with the reconstructed carrier to minimize common-mode current ripples. This, in turn, reduces the burden on common-mode chokes and the volume of common-mode chokes. Besides, the control structure of the emulator remains unchanged, and the emulator can achieve a plug-and-play feature. Experimental results are provided to validate the effectiveness of the proposed method.

Nowadays, more and more converters are interconnected face-to-face with each other to achieve higher power and equivalent switching frequency. This interconnected converter system appears in advanced testing benches for power electronics, paralleled-connected converters, or open-winding motor drive systems. Typically, the interconnected converters are powered by the same dc voltage source, thus inevitably creating a zero-sequence current path in the ac terminals. Consequently, undesired current harmonics, which do not exist in typical 3-phase 3-wire converter systems, are introduced, with increased power loss and extra stresses. These current harmonics have complicated frequency spectrum under different mission profiles, which have significant impacts on sampling results. However, these impacts of the current harmonics are seldom discussed. In this article, the time-domain models of the high-order zero-sequence current harmonics in an interconnected converter system are established under various operating conditions. Impacts of the high-order zero-sequence current harmonics, including current waveform distortions, sampling distortions, and control errors, are comprehensively identified and analyzed, which can help to predicate the current waveforms and eliminate the impacts of the current harmonics from more aspects. Simulations and experiments are provided to validate the analysis.

An electric machine emulator (EME) is becoming a popular solution to the characterization, testing, and validation of electric-machine-connected converters with complex mission profiles. Typically, a closed-loop current controller (CLCC) is implemented to regulate the current behaviors of the emulator. A high control bandwidth is necessary for the EME to ensure that the dynamic and high-frequency performances of the emulator are not distorted by the CLCC. However, the overenhanced control parameters of the CLCC will lead to compromised stability margin of the emulating converter. In this article, the limitations of typical control methods for the EME are analyzed, and a bandwidth-enhanced current control method, virtual-impedance control, is proposed to improve the dynamic performances and to expand the emulation range of the emulator. Compared with the typical control methods, the proposed approach is capable of enhancing the control bandwidth without increasing the control parameters or narrowing its stability margin. As a result, both the static and dynamic characteristics of the target electric machine can be accurately recreated, and the application range of the EME can be further extended. Experimental validations are conducted to demonstrate the effectiveness and superiority of the proposed control approach.

The capacitor is one of the key components in modular multilevel converter (MMC) systems. Its thermal characteristics have a significant impact on its lifetime and the reliability of the submodule. Various circulating current control strategies have been proposed to eliminate the second-harmonic circulating current or minimize the capacitor voltage ripple. However, the influences of these control methods on the capacitor thermal stress remain an unsolved problem. This article introduces a comprehensive loss and thermal model considering capacitor clusters inside the arm of the MMC. The thermal stress and distribution are analytically solved based on the mission profile of the MMC and capacitor parameters. Then, a circulating current control method for optimal thermal stress of capacitors is revealed by utilizing the proposed thermal model. Finally, simulation and experimental results based on a mission profile emulator for MMC capacitors are developed to verify the proposed method.

In order to perform advanced tests for the submodules (SMs) of modular multilevel converter (MMC) in a cost-effective and accurate way, mission profile emulation (MPE) technique is becoming a promising solution. MPE technique aims to test small number of SMs by emulating the mission profiles of MMC as testing conditions. However, a common problem for MPE is that when the SM works under nearest level modulation, the outputs of the SMs are voltage pulses or staircase-like voltages, which will severely disturb the testing current and further degrade the emulation accuracy for mission profiles. To suppress this disturbance, the existing methods mainly chose to utilize larger filter inductor or auxiliary circuit, which will inevitably increase the economic cost and complexity for testing system. As a result, this article proposes a suppression method to suppress the disturbances, and a parameter design method coping with suppression method to minimize the current distortion. With the proposed method, the mission profiles can be accurately and flexibly recreated without auxiliary circuits. Simulation and experimental verifications are provided to validate the proposed control and design method.

Modular multilevel converters (MMCs) are widely utilized in high-power applications, thereby advanced tests and validations of components of MMCs before field operations are becoming crucial. To achieve the tests and validations in a low-cost and efficient way, the concept of mission profile emulation (MPE) for the submodule (SM) of the MMC system has been proposed. However, most of the existing MPE methods are valid for the mission profile in steady states but cannot well emulate the dynamic mission profile in transient processes. Thus, when it comes to short-term overload tests where both the amplitudes and duration time of the dynamic mission profiles in transient processes need to be recreated accurately, the existing methods could fail to achieve this goal. In this article, the dynamic MPE is enhanced by embedding a virtual MMC system in the control strategy. The virtual MMC reshapes the dynamic responses of the emulated mission profile to resemble the responses of an actual MMC, which improves the emulation accuracy, especially in transient processes. Finally, simulation and experimental validations are given to verify the effectiveness of the proposed control strategy.

Online junction temperature (Tj) estimation for power semiconductor device insulated gate bipolar transistor is of great importance for reliability assessment and enhancement. Typically, Tj can be online calculated using the pre-calibrated correlation with on-state collector-emitter voltages (Vce) at loading current. However, the uneven temperature distribution inside the device during calibration is different from the conditions during operation. Uneven thermal distribution inside the device and self-heating of chips will cause significant estimation error by using the pre-calibrated Tj - Vce correlation, as the voltage drop on interconnections will be different. In this article, a novel calibration method of Tj - Vce relationship under pulsewdith modulation operation of device is proposed. By varying the switching frequency with fixed heatsink temperature, adjustable self-heating conditions and temperature distributions inside the device can be recreated. Moreover, a group of new relationships between junction temperature, heatsink temperature and temperature of interconnections inside device are revealed. By using the discovered relationship, the influence of uneven temperature distribution on Vce can be compensated in a noninvasive way, which can achieve higher accuracy in Tj estimation compared to the conventional method.

In high-power applications, power modules with multi-paralleled chips have been widely used. The reliability of power electronic devices is intimately tied to thermal characteristics, making the accurate thermal behaviors prediction of power modules with multi-paralleled chips crucial. The existing thermal coupling modeling for multichip power modules typically involves heating individual chips to extract thermal coupling parameters. However, the parallel-connected chips can only be heated simultaneously in the experiment. What is more, the large number of parameters and complicated characterization process in the existing models add challenges to practical applications. In this article, the thermal coupling effect has been analyzed in the frequency domain, and the chips with the same average input loss value are grouped in the characterization process. A frequency-domain thermal coupling model for power modules with multi-paralleled chips is proposed, enabling parameter extraction and thermal behavior prediction through both simulation and experiments. The method reduces the number of parameters and simplifies the characterization process of frequency-domain thermal coupling model without compromising the accuracy of the model compared to the existing methods. The proposed method has been validated through both finite element simulations and experimental measurements.

功率半导体器件的热应力是导致其失效的主要原因之一，因此近年来针对器件的热建模越来越受到关注。由于工况的复杂性，功率半导体器件承受的暂态电热行为通常呈现多时间尺度特性。为了解决这一问题，学者们做出了许多努力，而频域建模相对而言是一个较为简单且实用的方法。但是，目前大多数方法只针对器件的温度频域特性进行研究，而忽略了热流特性，导致器件热模型与外部散热条件相连时温度预测的不准确。文中从频域建模出发，分析功率半导体器件的热流在频域下呈现的低通滤波特性，并提出一种多阶三频率的低通滤波器的热流频域建模方法。该方法还原功率半导体器件全频段的热流特性，提升器件热应力描述的准确性，解决了器件模型与外部散热条件相连的难题，并通过有限元仿真和实验进行验证。

The fast development of distributed generations enables the microgrid a popular solution for the construction of the modern power grid, where the control behaviors of power electronics converters play a crucial role. Under this scenario, the emulation of microgrid control behaviors is becoming an emerging need for the testing and teaching of the AC microgrid. However, conventional approaches, such as the dynamic simulation test and the Power-Hardware-In-Loop, are still costly or bulky to flexibly recreate the correct characteristics of microgrid including different layers of controls and the interactions among multiple converters. The dynamic simulation test is bulky and costly to emulate various types of control behaviors since all physical components in the test system may need to be adjusted. The high cost of Power-Hardware-In-Loop is mainly caused by the high-performance real-time simulator and power amplifier. In this paper, a novel emulation system is proposed for the testing of the AC microgrid. A low-cost circuit configuration, which includes two face-to-face connected DC–AC converters and some passive loads, is introduced with the possibility of flexibly emulating most of the typical control schemes in an AC microgrid. In addition, a user interface for the real-time operation and measurement of the hardware platform is introduced on a host computer to further facilitate the testing process. Finally, various control schemes in microgrids, including the voltage control, current control, droop control, and secondary control, are validated in the experiment setup based on the proposed emulation approach.

The grid-connected converters are becoming an important role in modern power grid. The grid codes have been proposed for the operation of grid-connected converters. The low voltage ride-through, namely one of the grid codes, is the operation of grid-connected converters under grid fault. The reactive power is generated by gird-connected converters to support grid under low voltage ride-through operation. However, the maximum reactive power is restricted by the capacity of converter, which is designed for long-term operation. Since the low voltage ride-through is a short-term operation, the maximum output reactive power can be enhanced. An over-current low voltage ride-through operation is proposed, and it is designed based on the maximum short-term capacity. The maximum short-term capacity is designed to ensure the junction temperature of semiconductor devices in the converter under the reliable operation, which is calculated based on thermal analysis. Furthermore, the different approaches to enhancing the maximum short-term capacity is analyzed.

The high-power density design of the insulated gate bipolar transistor power module may lead to complicated thermal behaviors, and the thermal-coupling effect among multiple chips is a major focus in the field of thermal modeling and characterization. Unfortunately, the existing modeling methods simply describe thermal coupling effect as a superposition of temperatures caused by lateral thermal diffusion. In reality, it is not only the temperature of semiconductors which is important, but also of the heat flow characteristics in heat transfer process. In this article, the thermal coupling effect has been explained in another perspective that it is the result of the overlap between heat flow paths. Frequency domain analysis of heat flow has been first conducted by finite-element methods simulations, and a novel thermal model considering the heat flow coupling has been proposed. This approach focuses on the thermal modeling of the heat coupling effect in cooling system and greatly simplifies the thermal modeling of the heat coupling effect inside power module because it has been discovered that the coupling region is mainly contained in the section from the baseplate to the heatsink. As a result, the proposed method has the advantage of not only having some physical meaning, but also having a relatively simple modeling and characterization process when compared to existing methods. The proposed thermal coupling model is verified by both simulation and experiment, and the application for electrothermal simulation of electric machine drive complex mission profiles composed of multitimescale thermal dynamics is also provided.

With the growing demand for highly reliable power electronic systems, the degradation diagnosis of the power modules is becoming increasingly important. Due to its multilayer structure and complex operating conditions, power modules are subject to several different degradation mechanisms and locations. However, most existing approaches for degradation diagnosis are designed to identify only one particular type of degradation. In this article, a novel approach for diagnosing degradations in power modules is proposed based on the frequency-domain heat flow spectrum analysis. Different degradation modes can be clearly distinguished based on the discovery that the frequency-domain heat flow characteristics will change in different frequency bands under different locations of degradation. Simulations and experiments are provided to validate the proposed analysis and method.

Many efforts have been devoted to describe the multi-timescale thermal dynamics of power modules and frequency-domain modeling is a relatively new approach. Unfortunately, only the frequency-domain response of thermal impedance has been studied in recent works, so the existing models can only describe the temperature behaviors of semiconductors. In the reality, it is not only the temperature of semiconductors which is important but also of other parts of the package. In this article, a novel perspective to study the thermal dynamics by analyzing heat flow behaviors is proposed. Frequency spectrum analysis in finite-element method simulation has been first used in this article, and it reveals that heat flow of the power semiconductor device behaves as a multi-layer low-pass filter (LPF). As a result, a novel modelling method of heat flow with a 7order-3frequencies LPF has been developed in this article and it can provide a comprehensive description of heat flow behaviors for power modules at full bandwidth. Meanwhile, the effects on heat flow behaviors brought by boundary conditions are also considered to ensure that the proposed model can be easily adapted to different boundary conditions. The effectiveness and accuracy of the proposed model has been verified by both simulations and experiments.

The virtual synchronous generator (VSG) control is a promising solution for the grid-forming converters to enhance the inertia of the converter-based power grid. The virtual inertia and output impedance of the VSG are the important behaviors to be focused. However, the virtual inertia of grid-forming converters may cause active power oscillation due to the interaction with the power inertia of grid through the low-frequency band grid impedance. Besides, the resonance can be also triggered by the interaction between middle-frequency impedance of power grid and output impedance of converter. In order to test the stability of grid-forming converter, accurate emulation of grid behaviors from more aspects, including inertia and impedance under wider frequency ranges, is becoming critical. This article proposes a grid emulation method to mimic the inertia and impedance characteristics of power grid, targeting for the stability test of grid-forming converter under multifrequency bands. A high-switching-frequency converter and a low-switching-frequency converter are adopted in the proposed emulator structure to achieve both high capability in respect to control bandwidth and power level. Moreover, the virtual impedance control is integrated with the VSG control to emulate the line impedance and inertia within relatively wider frequency ranges. The realization of virtual impedance is achieved without derivation terms nor low pass filter. Finally, the performance of the proposed emulator is verified by various simulations and experimental measurements.

Active thermal controls (ATCs) are becoming an efficient solution to enhance the reliability of power electronics components and systems. In the applications of electric machine drive, ATCs under abnormal conditions, such as overstress in a relatively short timescale, still need further investigations. As one of the control freedoms, the dc voltage has a strong impact to the loss and thermal behaviors of power semiconductor devices. In this letter, the loss and thermal characteristics under the stall condition of the electric machine drive converter are investigated, and an ATC method with Adaptive dc voltage control (ADVC) is proposed. By using the proposed ADVC, the conduction loss and switching loss of the power devices are redistributed intentionally, so that the total power loss and junction temperature under the stall condition can be minimized. Furthermore, a speed-based-coefficient digital filtering algorithm is applied for dc voltage reference calculation, so that the ADVC performs self-adaptive to the rotor speed and be integrated into the original control structure of the drive converter. Simulations and experimental results are provided to validate the effectiveness of the proposed method.

The grid-connected converters are becoming a fundamental building block in the modern power grid, and the stability of grid-connected converters, especially when they are connected to weak grid, has drawn increasing attention. In order to test the interaction with various grid impedances and validate the stability behaviors, more accurate and advanced emulation of grid impedance is becoming an emerging need. However, the existing approaches are still difficult to flexibly shape the grid impedance under medium-to-high frequency range. In this article, a novel configuration for programable impedance emulation of power grid is proposed. The proposed grid emulator is composed of two power electronics converters with special control functions, i.e., the impedance forming converter (IFC) and power supporting converter (PSC). The IFC is designed with a higher switching frequency to virtually emulate different grid impedances under medium-to-high frequency band. On the other hand, the PSC is designed with a lower switching frequency to generate/absorb the power of the converter under test. Besides, a Norton-circuit-based virtual impedance control strategy is introduced to eliminate the derivation term in the control structure of virtual impedance. Finally, the performance of the proposed emulator is verified by various simulations and experimental prototype.

Active thermal control (ATC) is becoming a popular solution to improve the reliability of power semiconductor devices in electric machine drive systems. Conventional ATCs mostly focus on the extension of a lifetime under common mission profiles in relatively long-term timescale, but the ATCs under abnormal conditions, such as extreme overstress in relatively short-term timescale, still need further investigation. This letter proposes a novel ATC method by optimal phase angle to redistribute the electrothermal stress under the stall condition of the machine drive inverter. During the normal operation, the proposed method will not disturb the original drive control structure. During the stall condition, the maximum electrothermal stress in power semiconductor devices can be relieved significantly. With no extra fluctuating electromagnetic torque, mechanical stability can also be guaranteed. Simulations and experimental results are provided to validate the effectiveness of the proposed method.

In the last decade, significant progress has been made in electrification, especially in the applications of electrical vehicles, renewable energies, and industry automations, which imposed much more complicated working conditions to electric machines as well as the drive converters. More advanced features, such as the control strategies, functionality, stability, and reliability of machine drive systems, need to be characterized and validated. Thus, there is an emerging need to accurately recreate the behaviors of electric machine drive systems from more aspects for comprehensive tests. This article aims to foster and investigate the mission profile emulation technologies for the testing of electric machine drive systems. The key factors of the system to be emulated are first clarified, and then different testing concepts are summarized and compared, including dynamometer test, controller hardware-in-the-loop simulation, power hardware-in-the-loop simulation, and power-electronics-based emulation. The features of power-electronics-based emulation, which is considered as a promising trend, will be further discussed with respect to the degrees of coupling with the drive converter, electric machine models, and control structures. Finally, challenges in the field of mission profile emulation for electric machine drive systems are discussed.

For modular multilevel converter (MMC) under Nearest Level Control (NLC) with dozens of or less sub-modules (SMs), circulating current suppression control (CCSC) can lead to severe fluctuation in dc current of MMC due to insufficient voltage levels to modulate the control voltages generated from circulating current suppression. This article presents a detailed analysis of the mechanisms of the above-mentioned problems, and a solution by using a dual-mode modulation method combining pulsewidth modulation (PWM) and NLC modulation is presented. In this method, two SMs in each arm are selected to operate under PWM modes to precisely modulate the control voltages from circulating current suppression, and the rest of SMs are operated under NLC modes to roughly modulate the output ac voltage of MMC. A voltage balancing control method for both of the two different modulated SMs is also investigated. The proposed method not only eliminates the dc current fluctuation in MMC, but also achieves voltage balancing among SMs. Finally, validation by RTDS is given to verify the effectiveness of the proposed method.

Insulated gate bipolar transistor (IGBT) modules with multiple chips have wide range of applications, and the correct estimation for the thermal behaviors inside IGBT modules is becoming crucial. Thermal impedance matrix is one of the most adopted approaches to describe the thermal-coupling effect of IGBT module. For simplicity of analysis, the heatsink or ambient temperature is typically chosen as the reference node for the thermal-coupling impedance term, while the case temperature is simplified or ignored. This letter provides a thermal coupling model enabling case temperature as reference node. This proposed model decouples the thermal coupling impedances of IGBT module itself and external cooling condition, so that the modeling of cooling conditions outside device and inside the power module, can be separately considered. The characterization method and advantages of the proposed model are verified by an experimental demonstration, and the potential applications are further discussed.

在柔性直流输电系统中,变流器的稳定可靠运行对整个输电系统具有重要意义。考虑到目前模块化多电平变流器(MMC)在柔性直流输电中的应用愈加广泛,且MMC中组成元件数量众多、工况复杂,因此有必要在投运前对MMC的设计及控制进行深入验证。为了实现准确有效的功能性和可靠性测试,需要对MMC的关键部件施加与实际工况相近的运行条件。然而传统MMC测试方法成本代价较高,且测试自由度受限,相比之下,新出现的工况模拟测试方法可基于简化电路对较少的MMC子模块单元施加贴近实际工况的应力条件和控制行为,因此可以极大地提升测试效率。首先,介绍了MMC子模块工况模拟测试的概念和意义。然后,介绍了多种适用于MMC子模块工况模拟方法,分析对比了各方法在测试成本与模拟精度上的区别。最后,结合实际案例,通过仿真和实验验证了MMC子模块工况模拟方法的可行性和潜在价值。

模块化多电平变换器(MMC)子模块电容需要承受巨大的桥臂电流冲击,是系统中失效率最高的元件。等效串联电阻(ESR)是表征电容健康状态典型参数之一。通过对电容ESR进行监测,可对电容损耗、温升以及寿命进行估计,从而实现电容的预测性维护和替换,这对提升MMC系统电容的可靠性能有重要价值。在此基于MMC子模块电容电压的正负跳变特征,提出了电容ESR在线监测方法:通过检测子模块电容由于ESR存在导致的正负电压双跳变沿和流入子模块的桥臂电流计算出电容ESR;通过实验分析验证了所提方案的有效性。

近年来,模块化多电平变换器(modularmultilevel converter,MMC)可靠性问题越来越受到关注。电容作为组成MMC系统子模块的重要元件,因运行时需承受较大桥臂电流冲击和电压波动,成为MMC系统中失效率最高的元件之一。对电容值进行状态监测(condition monitoring,CM),对于提升电容运行可靠性,并实现高效的可预测维护具有重要意义。文中建立MMC系统子模块电容电压时域数学模型,推导出子模块电容值的新型计算方法,通过采样工频周期内4个特定时刻的电容电压实时监测MMC子模块电容值。通过搭建MMC子模块的工况模拟系统,对所提方法进行实验分析,验证所提方法的有效性。

Electric machine emulation (EME) is becoming a popular solution in advanced testing and validation of power-electronics-based machine drive systems. In terms of a typical EME, the stator current references are first calculated in response to the sampled terminal voltage, and then, are electrically generated by power electronics converters. In this type of structure, closed-loop current control and low-pass sampling for the voltage are inevitably introduced, resulting in distortion in frequency-domain behaviors of EME. Consequently, the steady-state performance under a high fundamental frequency, and the dynamic performance under load transients, may deviate from those of the target machine system. In this article, the bandwidth limitations of the typical EME are identified and analyzed in detail, and a novel structure that realizes full-bandwidth mission profile emulation is proposed. Theoretical analyses are given to prove that the frequency-domain characteristics of the proposed structure would be identical to the actual machine systems, which allows for the extended operating range of mission profile emulation. Simulation and experimental results are provided to validate the effectiveness of the proposed method.

Mission profile emulation (MPE) for submodules (SMs) in the modular multilevel converter (MMC) is a crucial step before a full-scale system is put into field operation. Existing methods suffer from limitations of the testing accuracy due to the staircase-like arm voltages that result in distorted loading current and require large filter inductance. This is especially the case when a limited number of SMs are under test. In this article, an efficient MPE method is proposed to emulate the loading behaviors of multiple SMs in MMC. The testing circuit allows two arms of MMC with flexible SM number, operating in inverting and rectifying mode under nearest level modulation, to be tested simultaneously with reduced dc supply voltage. A common H-bridge circuit is introduced in the testing circuit, with each arm of the H-bridge circuit functioning as the voltage compensator by using feedforward control. In this way, the current distortion can be significantly suppressed, and testing accuracy can be guaranteed in a cost-efficient manner even though no large inductor is included in the testing circuit. The proposed method allows SMs under test to be loaded as in the actual back-to-back MMC system. Simulations and experimental measurements are given to validate the proposed method.

Modular multilevel converter (MMC) is one of the most promising converter topologies for medium/high-voltage applications, where the nearest level modulation (NLM) is widely applied. However, the capacitor voltage balancing methods under this modulation mode exist some inefficient actions, which are useless for capacitor voltage balancing but lead to unnecessary switching of power semiconductor devices. In this article, the disturbance and unbalance mechanisms of capacitor voltages in MMC under NLM are analytically revealed and solved. The disturbing metrics for capacitor voltage are digitally extracted to identify the accurate time interval in which the switching actions have immediate effects on capacitor voltage balancing. Then, a demand-oriented scaling factor is introduced to adjust the balancing strength by changing the range of the time intervals which are highly efficient with respect to capacitor voltage balancing, thus flexible tradeoff between the switching frequency of power semiconductor devices and the balancing level of capacitor voltages can be achieved. Finally, a dedicated mission-profile-emulator for the testing of MMC is designed and built with comprehensive validations to verify the effectiveness of the proposed method.

The mission profile emulator (MPE) proves to be an effective and cost-efficient approach to validate the design and reliability of the submodule (SM) in a modular multilevel converter (MMC). This article established the detailed models for the capacitor voltages of SM in the MMC system. The factors that can determine the dc component of capacitor voltages in SM of MMC are analytically solved. The difference between the capacitor voltage of SM in a complete MMC system and that of SM in MPE is discovered, explained, and verified. In order to improve the emulating accuracy for the capacitor voltage in SMs of the MPE, a novel voltage control method, which is more adaptive to the operating conditions of MMC, is proposed. The simulation models and experimental setup are built to verify the validity of the proposed methods.

The mission profile emulator (MPE) proves to be an effective and cost-efficient tool to validate the design and reliability of the submodule (SM) in a modular multilevel converter (MMC). However, the low-frequency and random switching behaviors of SMs in the MMC with nearest level modulation (NLM) undermine the testing accuracy of MPE in many aspects, including the large ripples in the loading current and the lack of flexibility in control dynamics. To tackle these problems, a MPE with special control structure is introduced in this article to test the individual SM modulated with NLM. The proposed testing method is realized with a common single-phase configuration and the current ripples are suppressed by separating the control functions for two arms in a full-bridge circuit. What's more, the proposed approach gets rid of the need for historical gating signals of the SM under test, and offers a virtual control method to autonomously generate the SM gating signals that can realize the self-balancing of capacitor voltage and the emulation of NLM behaviors in MMC system. Simulations and experimental measurements are also given to validate the proposed method.

随着可再生能源不断开发,电力电子系统的运行条件愈发严苛,对功率半导体器件的可靠性提出了严峻的挑战,其中,严苛的环境温度及器件温度的快速变化是影响功率器件寿命的2个主要因素。因此,模拟环境温度对功率器件的影响是分析器件老化因素的关键步骤。由于传统模拟环境温度的方法昂贵且不能模拟温度的急剧变化,因此提出了一种功率半导体器件的温控散热器设计方法。该设计方法引入了基于PLECS的热仿真模型及基于占空比可变开关信号的温度控制算法,能够实现功率半导体器件环境温度的模拟。相较于传统方法(如温箱),该方法能够实现更快的温度响应速度,且成本更低。搭建了实验样机,通过实验验证了该设计方法的有效性。

高效、准确、可重复地提取功率半导体器件的温度特性并构建其热阻抗模型,对于电力电子系统的可靠性研究和热设计具有重要意义。为有效提取功率半导体器件的热阻抗特征参数,结合现有功率半导体器件热阻抗测试相关国际标准,提出了一种新型热阻抗测试系统及控制策略,通过使用数字信号处理器DSP (digital signal processor)控制器及温控散热器共同实现了高效准确的热阻抗测量,并且实现了测试过程的自动化。搭建实验样机,验证了测试系统及控制方法的有效性和可重复性。

Nowadays, more and more converters under voltage control mode with LC filter and current control mode with L/LCL filter are interconnected, forming a more complicated impedance network and resulting in coupled control behaviors. This type of interconnected converter system can be commonly seen in a stand-alone microgrid and some advanced testing benches for power electronics converters. In this article, a system consisting of a voltage-controlled converter with LC filter and a current-controlled converter with LCL filter have been studied. A detailed mathematical model is proposed to describe the stability and coupling characteristics of such system. It is found that the stability problem in this type of configuration may arise in an uncommon way, which is different from the typical resonance in a grid-connected converter system and can be triggered in higher frequency band. Meanwhile, the voltage and current behaviors of interconnected converters are strongly coupled through the complicated filter impedances and control loops in low-frequency band and mid-frequency band.

High penetration of distributed generations and active loads have enabled the power electronics converter to become a vital component in the modern power grid system, and the broad employment of grid-connected converters at various power levels is making the grid impedance and characteristics complicated. Consequently, in order to validate more advanced features such as the reliability and stability performances of the grid-connected converters, it is becoming an emerging need to emulate the grid behaviors from more aspects. This article serves to foster and investigate the state-of-the-art techniques in the field of ac grid emulation from the perspective of multiple spatial-scales and multiple time-scales. Four major concepts used for grid emulation with featured principles, including concept I (analog simulation with under-scaled components), concept II (grid characteristics in the real-time simulator), concept III (grid characteristics in the converters structure), and concept IV (grid characteristics in the converters controller), are summarized, respectively, in this article. The practical implementation regarding to the circuit topology and the power supply for the grid emulation system are also discussed. Finally, the future trends and conclusions in the field of ac grid emulation are provided.

The resonance of LCL filter gives challenge to the control stability of LCL-filter-based converter systems. To suppress the filter resonance, damping methods are widely adopted. Nevertheless, the determination of damping parameters for LCL filters can be vague, insufficient or excessive, because the filter resonance is affected by multiple factors. Furthermore, due to the effect of damping resistor, the attenuation of switching-frequency current ripple may vary from the expected value, and thus, can lead to unwanted iterations to ensure proper filtering performances. The purpose of this article is to provide an efficient and accurate design method for the damping in LCL filters. A metric of “critical damping ratio” is introduced and solved for the first time. With the critical damping ratio setting at 0.28, the resonance peak on the magnitude-frequency curve of LCL filter can be precisely flattened without introducing unnecessary damping losses, and the grid-side inductor and damping resistor can be designed in an accurate and less iterative way. Moreover, a “peace-of-mind” stability performance of LCL filter can be also achieved. The simulation and experiment results are provided to verify the analysis.

Modular multilevel converter (MMC) may contain a large number of submodules (SMs). The overall reliability of MMC strongly relies on the comprehensive testing and validation of SMs. However, building a relatively complete MMC system/arm for the testing of SMs is time-consuming and costly. In this article, mission profile emulator (MPE) for individual SM of MMC is presented along with the design and control methods. By the proposed schemes, the complete electrical characteristics including the load current and capacitor voltage of SM under test can behave closely to the actual SM in an MMC system. Moreover, the current ripple, which is an important loading factor for SM, can be accurately designed and restrained. Both the simulation and experimental results are provided to validate the effectiveness of the proposed methods.

The modular multilevel converter (MMC) is an attractive converter topology for medium-/high-voltage applications. The voltage balancing for floating capacitors of submodules in MMC under carrier-phase-shift pulsewidth modulation (CPS-PWM), is an important research focus. However, the existing capacitor voltage balancing methods under this modulation mode have limited robustness and may not be applied to different working conditions. In this article, the disturbance and unbalance mechanisms of capacitor voltages in MMC system under CPS-PWM are theoretically revealed and solved. The disturbance metrics for capacitor voltage are extracted by using a proposed asynchronized sampling mode. Based on the characteristics of the extracted disturbances in nonsynchronized sampling mode, a novel capacitor voltage balancing method is proposed. The proposed balancing method is highly efficient for different working conditions of MMC, and is easy to be designed/realized. Finally, a flexible mission-profile emulator for the test of MMC is designed and built, with comprehensive validations to verify the effectiveness of the proposed capacitor balancing method under different operating conditions of MMC.

This article proposes a highly efficient mission profile emulator (MPE) for submodules (SM) in modular multilevel converter (MMC), with respect to its basic circuit topology, control method and design. By using a common three-phase dc–ac power converter, as well as some analytical equations of MMC, the proposed MPE is capable of emulating operating conditions of multiple SMs in the MMC system. Compared with existing single-phase testing methods, the proposed three-phase structure achieves better testing efficiency. In the proposed MPE, two testing units of SMs, including four different mission profiles of submodule, are tested simultaneously with low requirements on dc power supply voltage. The comparisons between the complete MMC system and the MPE in the simulation, as well as experimental measurements, are given to verify the validity and accuracy of the proposed testing approach.

Based on the finding that the gain of heat flow inside a power semiconductor device behaves as a low-pass filter (LPF) under the frequency domain, an advanced thermal model developed in the frequency domain has been proposed in recent years. The main advantage of this model is that it can analyze the multitime scale thermal dynamics of power semiconductor devices under complex mission profiles. However, the critical frequencies in the LPF of this frequency-domain thermal model are still difficult to be accurately extracted, thus leading to inaccuracy in the predicted thermal behavior. In this article, the correlation between the first thermal path and the second thermal path in the frequency-domain thermal model has been comprehensively analyzed and modeled, and a new method to determine the critical frequencies is thereby proposed. The simulation and experimental results have been provided to verify the effectiveness of the proposed modeling and characterization method.

Advanced loss characterizations of power semiconductor devices are becoming crucial for the reliability evaluation and improvement of power electronics systems. In this letter, a method based on an H-bridge testing circuit is proposed to reveal the statistical distribution of switching energy and on-state voltage of power semiconductor devices. This method includes a specially designed testing sequence for multiple devices under test, as well as the statistical representation of loss-related characteristics. By the proposed method, the loss-related characteristics of multiple transistors and freewheeling diodes can be evaluated in multiple times, and the testing conditions are closer to the working conditions of devices in practical use compared to the conventional double-pulse test. Based on the experimental results, the probability density function for the switching energy and on-state voltage can be further generated, which enables more correct prediction for the thermal and reliability performances of power semiconductor devices.

Frequency-domain modeling is a relatively new approach for thermal impedance description of power semiconductor devices, and it has shown promising advantages to analyze the multitimescale thermal dynamics of power semiconductor devices under complex mission profiles. However, parameters in the frequency-domain thermal model are still difficult to be accurately extracted, and sometimes the extraction process would be complicated and ambiguous depending on the construction of power devices and heat sink. This article proposes a new method to identify these key parameters of the frequency-domain thermal model for power semiconductors. The proposed approach utilizes the information of heat flowing out of device and only requires temperature responses of three different locations in the heat path of insulated-gate bipolar transistor (IGBT) module under a step power-loss. By the proposed approach, the critical frequencies in the frequency-domain thermal model of IGBT module can be extracted more easily and accurately. The effectiveness of the proposed method is also validated by simulations and experiments.

Power-electronics-based emulators have been showing promising prospects in advanced testing of various applications of power electronics systems. For electric machine applications, typical machine emulators calculate the references of stator current in response to terminal voltages via mathematical models of the machine system, and then, the current behaviors of emulators are regulated by using feedback controls. However, the dynamic and high-frequency performances of these machine emulators could be distorted by the introduced control loops, thus compromising the emulating performances. In this article, the limits of typical machine emulators are analyzed, and a new approach is proposed for the real-time emulation of permanent magnet synchronous machines (PMSM). A linear regulator without feedback control loop is proposed and designed to reshape the frequency-domain characteristics of the converter and current filter inside the emulation system. Compared with typical solutions, the proposed approach has frequency-domain characteristics closer to the target PMSM. The dynamic performances can be more accurately recreated, and the applicable frequency range for emulation can be extended. Simulations and experimental validations are also conducted to verify the effectiveness of the proposed approach.

Modular multilevel converter (MMC) has been widely used in medium/high-voltage direct current transmission, motor drive, and renewable energy power generation. The reliability requirements of the MMC system, which is composed of numerous sub-modules (SMs) as building blocks, are getting crucial. However, the testing for reliability of SMs in a full MMC system is time-consuming and costly. In this paper, a mission profile emulator for SMs in the MMC system is therefore focused; by using this mission profile emulator, the SMs can be tested individually without building a full MMC system. Simulation results have shown that arm current and capacitor voltage of the SM under test agree well with the SM in a complete MMC system. A scaled-down experimental platform is built and experimental results have proved the validity of this emulator.

由数字信号处理器(DSP)与现场可编程逻辑阵列/复杂可编程逻辑器件(FPGA/CPLD)混合芯片构成的新型控制器,因其结构灵活,输出功能丰富,是目前电力电子领域较常用的一种控制器方案。这种控制器架构可以将采样与控制运算及脉宽调制(PWM)与输出两部分主要功能通过不同芯片实现。针对DSP+FPGA/CPLD控制系统中的这些多芯片、多控制器的协调同步问题进行研究,采用DSP发送同步信号的方式来解决多芯片和多控制器间的协调同步问题,最后通过实验验证了该方法的有效性。

This article proposes a testing method for multiple submodules (SMs) in a modular multilevel converter (MMC), along with its topology, control strategy, and basic design. The proposed testing method is capable of emulating the operating conditions of multiple SMs both in rectifying and inverting modes of the back-to-back MMC system. The configuration of the testing system significantly reduces the requirements for the dc supply voltage and is independent of the numbers of tested SMs. In the proposed testing approach, analytical equations are introduced in the control loop in order to emulate the dynamic mission profiles of SMs. The comparisons between the MMC system and the testing method in the simulations, as well as the scaled-down experimental setup, verify the validity and accuracy of the proposed testing approach.

This letter proposes a thermal characterization method of power semiconductor devices based on an H-bridge testing circuit, as well as its corresponding control and measurements. In the proposed method, the power semiconductor devices under test (DUTs) operate under the switching mode, which is closer to the practical use. Due to the presence of switching loss, similar ranges of junction temperature can be achieved with much lower heating current than the one in the conventional testing method. Besides, a current controller is used to cut off the heating current rapidly, so that the proposed method can approximate an ideal step power loss and thus contribute to more accurate estimation of thermal impedance. In addition, the proposed testing method enables multiple DUTs and repeated measurements, in order to take parameter distribution and uncertainty into account. The feasibility, control, and some electrical behaviors of the proposed method are verified through experimental tests.